1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com vn2410 features free from secondary breakdown low power drive requirement ease of paralleling low c iss and fast switching speeds excellent thermal stability integral source-drain diode high input impedance and high gain applications mot or controls converters ampli?ers switches power supply circuits drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) ? ? ? ? ? ? ? ? ? ? ? ? ? general description this en hancement-mode (normally-off) transistor utilizes a vertical dmos structure and supertexs well-proven, silicon- gate manufacturing process. this combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coef?cient inherent in mos devices. characteristic of all mos structures, this device is free from thermal runaway and thermally-induced secondary breakdown. supertexs vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. n-channel enhancement-mode vertical dmos fet absolute maximum ratings parameter value drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 20v operating and storage temperature -55 o c to +150 o c soldering temperature* 300 o c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. * distance of 1.6mm from case for 10 seconds. ordering information device package option bv dss /bv dgs (v) r ds(on) (max) () i d(on) (min) (a) to-92 vn2410 VN2410L-G 240 10 1.0 -g indicates package is rohs compliant (green) to-92 (l) ga te source drain yy = year sealed ww = week sealed = green packaging s i v n 2 4 1 0 l y y w w to-92 (l) product marking pin con?guration package may or may not include the following marks: si or
2 vn2410 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com electrical characteristics (t a = 25 o c unless otherwise speci?ed) sym parameter min typ max units conditions notes: ? i d (continuous) is limited by max rated t j . thermal characteristics switching waveforms and test circuit 90% 10% 90% 90% 10% 10% puls e genera to r v dd r l outpu t d.u.t . t (on) t d(on ) t (off) t d(off) t r inpu t input output 10 v v dd r ge n 0v 0v t f bv dss drain-to-source breakdown voltage 240 - - v v gs = 0v, i d = 100a v gs(th) gate threshold voltage 0.8 - 2.0 v v gs = v ds , i d = 1.0ma i gss gate body leakage - - 100 na v gs = 20v, v ds = 0v i dss zero gate voltage drain current - - 10 a v gs = 0v, v ds = 120v - - 500 v gs = 0v, v ds = 120v, t a = 125c i d(on) on-state drain current 1.0 - - a v gs = 10v, v ds = 15v r ds(on) static drain-to-source on-state resistance - - 10 v gs = 2.5v, i d = 100ma - - 10 v gs = 10v, i d = 500ma r ds(on) change in r ds(on) with temperature - 1.0 1.4 %/ o c v gs = 10v, i d = 500ma g fs forward transductance 300 - - mmho v ds = 10v, i d = 500ma c iss input capacitance - - 125 pf v gs = 0v, v ds = 25v, f = 1.0mhz c oss common source output capacitance - - 50 c rss reverse transfer capacitance - - 20 t r rise time - - 8.0 ns v dd = 60v, i d = 400ma, r gen = 25 t d(on) turn-on delay time - - 8.0 t f fall time - - 24 t d(off) turn-off delay time - - 23 v sd diode forward voltage drop - 1.2 - v v gs = 0v, i sd = 190ma notes: all d.c. parameters 100% tested at 25 o c unless otherwise stated. (pulse test: 300s pulse, 2% duty cycle.) all a.c. parameters sample tested. 1. 2. package i d (continuous) ? (ma) i d (pulsed) (a) power dissipation @t c = 25 o c (w) jc ( o c/w) ja ( o c/w) i dr ? (ma) i drm (a) to-92 190 1.7 1.0 125 170 190 1.7
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry an d specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//ww w. supertex.com ) ?2009 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 te l: 408-222-8888 www .supertex.com 3 vn2410 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-vn2410 b120709 3-lead to-92 package outline (l) symbol a b c d e e1 e e1 l dimensions (inches) min .170 .014 ? .014 ? .175 .125 .080 .095 .045 .500 nom - - - - - - - - - max .210 .022 ? .022 ? .205 .165 .105 .105 .055 .610* jedec registration to-92. * this dimension is not speci?ed in the jedec drawing. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc.#: dspd-3to92n3, version e041009. seating plane 1 2 3 front v iew side v iew bottom v iew e1 e d e1 l e c 1 2 3 b a
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